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SMBus/I 2 C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Pin Description
QSOP
1
2
PIN
TQFN
15
16
NAME
V LA
AD0
FUNCTION
Port Supply for P1–P9. Connect V LA to a power supply between 1.62V and 5.5V.
Bypass V LA to GND with a 0.047μF ceramic capacitor.
Address Input. Sets the device slave address. Connect to GND, V DD , SCL, or SDA to
provide four address combinations.
Reset Input. RST is an active-low input, referenced to V DD , that clears the 2-wire interface
3
1
RST
and can be configured to put the device in the power-up reset and/or to reset the PWM
and blink timing.
4
5
6
7, 8, 9,
11, 12, 13
10
14
15
16
—
2
3
4
5, 6, 7,
9, 10, 11
8
12
13
14
EP
P1/ INT
P2/OSCIN
P3/OSCOUT
P4–P9
GND
SCL
SDA
V DD
EP
Input/Output Port. P1/ INT is a general-purpose I/O that can be configured as a
transition detection interrupt output.
Input/Output Port. P2/OSCIN is a general-purpose I/O that can be configured as the
oscillator input for PWM and blink features.
Input/Output Port. P3/OSCOUT is a general-purpose I/O that can be configured as the
PWM/blink/timing oscillator output for PWM and blink features.
Input/Output Ports. P4–P9 are general-purpose I/Os.
Ground
Serial-Clock Input
Serial-Data I/O
Positive Supply Voltage. Bypass V DD to GND with a 0.047μF ceramic capacitor.
Exposed Paddle on Package Underside. Connect to GND.
6
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